1. Field of the Invention
The present invention relates to electronic circuits and, more particularly, to digital clock synthesizers.
2. Description of Related Art
In applications that require a generated clock signal, a digital clock may be synthesized using a digital synthesizer. A conventional digital synthesizer is generally controlled by a high frequency clock and is used to generate a lower frequency clock. The frequency ratio between the generating clock and the generated clock is typically at least two. The generated clock may have some variation in each generated period due to the discrete sampling effect of the generating clock. But, the resulting synthesized clock will have an output pulse stream that is cyclic over some period of time, resulting in a consistent average frequency. If this output stream is averaged or filtered (such as using analog devices) then the output clock will have a more even period from cycle to cycle. Nevertheless, certain applications or situations require the output clock to be adjusted or tuned. For example, the clock may need to be tuned to align with other system components or to account for delays in the system clock distribution.
A programmable delay line is one conventional apparatus for tuning the output phase of a digital clock. A conventional programmable delay line includes a number of signal-passing elements that are connected to the output of a clock synthesizer. The signal-passing elements are connected in series such that the signal from the clock synthesizer is delayed by a small amount after passing through each element. The delay line includes a delay selection that has an input from the delay line after each signal-passing element. Accordingly, the clock output may be generated from different places in the delay line using the delay selection. The phase of the clock output may be changed depending on the location in the delay line from which the clock output is generated.
The conventional programmable delay line has a number of disadvantages and limitations. One disadvantage is that, because the length of a delay line is naturally limited, the range over which the phase may be changed is also limited. Another disadvantage is that, because there is a limit to the delay step size, the amount of phase change is also limited. Another limitation is that the amount of delay is not constant. Due to the nature of the components of a delay line, the amount of delay varies with, for example, temperature, power supply voltage, manufacturing process and other environmental conditions. Furthermore, because a delay line has a finite start and end, the delay line can run out of range. For instance, a user may not be able to select the desired clock output phase if the delay has to be either earlier than the start of the delay line or later than the end of the delay line.
Accordingly, there is a need for a technique for controlling the phase of a clock output over a wide range and with variable step size that ensures consistent performance over all process, voltage and temperature ranges.